Field of the Invention
The invention relates to a bipolar comparator containing an asymmetric differential amplifier stage.
Comparators are circuit configurations, which have been generally known for a long time so only the basic configuration and the operation of such a comparator will be discussed in the text, which follows.
Comparators are generally used for detecting a voltage referred to as a reference potential. As soon as the voltage to be detected exceeds a predetermined value, the so-called threshold value, a signal can be picked up at the output of the comparator, which indicates that the threshold value, which for example, can be the reference voltage, is exceeded. If, in contrast, the threshold value is not reached by the input voltage at the comparator, the output of the comparator outputs an output signal which also unambiguously signals a falling short of the threshold value. In the case of a comparator having an asymmetric output, two inputs and a single output are provided. At the output terminal, two different voltage levels can be picked up depending on whether the input voltage applied to the input terminals is greater than or less than the reference voltage.
A standard version of a bipolar comparator exhibits a differential amplifier at its input, which has two bipolar transistors, the load paths of which are connected to input terminals for applying an input voltage at an emitter end. The comparator typically has an offset xcex94Vbe, Vbe being a voltage between a base and an emitter of the bipolar differential amplifier transistors.
The problem with such bipolar comparator circuits is the fact that at the collector terminals, leakage currents flow, which can change an amount of an offset xcex94Vbe in an undefined manner. The offset xcex94Vbe caused by the leakage currents is changed in a defined manner even if the leakage currents occurring in the two bipolar transistors are identical per unit area of the collector, that is to say there is optimum matching. However, the change in offset leads to a more or less great impairment of the accuracy of the comparator and can result in an operational failure of the comparator in the extreme case.
In conventional comparator configurations, therefore, it is attempted to avoid the leakage currents at the collectors as much as possible or at least to reduce them, as a result of which, naturally, a compromise must be made in accuracy and thus also in operability of the comparator configuration. It is particularly in the case of very high temperatures, for example within a range of more than 150xc2x0 C. and/or a not inconsiderable injection of minority charge carriers into the semiconductor substrate, also called reverse current in the case of power semiconductors, that avoiding the leakage current is possible only to a certain extent or not at all. For this reason, it has hitherto been possible to use conventional bipolar comparator configurations based on avoiding leakage currents only to a restricted extent under the conditions described. However, there is a requirement to use existing comparator configurations even at higher operating temperatures and minority charge carrier injections.
It is accordingly an object of the invention to provide a bipolar comparator which overcomes the above-mentioned disadvantages of the prior art devices of this general type, which remains largely unaffected in its operability and accuracy even with high collector leakage currents.
With the foregoing and other objects in view there is provided, in accordance with the invention, a bipolar comparator with an asymmetric differential amplifier stage.
The comparator contains current sources including a first current source and a second current source each having an output and input terminals including a first input terminal for receiving a first input potential and a second input terminal for receiving a second input potential. Transistors, including a first transistor and a second transistor each having a control electrode short-circuited to one another, a load electrode, and a load path, are provided. The load path of the first transistor is disposed in series between the first current source and the first input terminal. The load path of the second transistor is disposed in series between the second current source and the second input terminal. A supply terminal for receiving a supply potential is connected to the current sources. An output terminal is connected between the second current source and the load electrode of the second transistor. An output signal is available for picked up at the output terminal. A third transistor is provided and has a load path disposed in parallel with the load path of the first transistor. The first transistor is connected as a diode resulting in a diode-connected first transistor. The first current source generates a first operating current being a multiple of a second operating current generated by the second current source and the multiple corresponds to an effective area ratio of the first and the third transistor with respect to the second transistor.
By connecting the additional transistor in parallel with a transistor of the differential amplifier stage and by a suitable choice of area ratios and of the currents, it becomes possible for the influence of the collector leakage currents on the accuracy of the offset voltage to be eliminated. The offset voltage is then largely leakage-current-independent over wide ranges of the operating current even with increasing temperature and has a defined temperature dependence that can be compensated for, for example, by a shunt resistor or similar circuit device. The essential prerequisite for this is, however, very good matching of the two transistors of the differential amplifier stage and of the additional transistor. The transistor added additionally which is also called a dummy transistor in the text which follows is thus only used for eliminating the leakage-current-dependence of the offset voltage. However, the dummy transistor has no influence whatever on the actual operation of the comparator.
It is essential for the operation of the comparator configuration according to the invention that the sum of effective or normalized collector areas of the diode-connected transistor and of the dummy transistor connected in parallel therewith is a multiple of the effective or normalized collector area of the respective other transistor of the differential amplifier stage. By effective (or normalized) collector area, the (normalized) boundary area between the collector and substrate is meant. The multiple also corresponds to the ratio of the operating currents of the two current sources. As already mentioned, the ratio of the currents provided by the two current sources should very precisely correspond to the effective collector area ratios. The effective collector area ratios are obtained from the corresponding area ratios of the first transistor and the dummy transistor divided by the collector area of the second transistor.
In a very advantageous embodiment of the invention, a correction circuit is provided which essentially contains two current balancing circuits. The outputs of the current balancing circuits are connected to in each case one of the current sources so that a correction current can be superimposed on the operating current generated by the respective current sources. In the case where at least one leakage current exceeds the operating current of the respective current source, it is just this operating current on which a correction current is superimposed in such a manner that the sum of the currents is greater in every case than the corresponding leakage current. This makes it possible to ensure that the current through the load path of the differential amplifier transistors is greater in every case than the corresponding leakage current. Thus, no unwanted and abrupt rise in offset voltage can occur. By the correction circuit, the operating current supplied to the two transistors of the differential amplifier stage can be dynamically adapted.
In a particularly advantageous embodiment, the two current balancing circuits of the correction circuit have in each case a single common input branch. In the input branch, a measuring transistor is advantageously disposed which measures the respective leakage current of the comparator configuration. The measuring transistor is only used as a sensor and typically does not need to match the area ratios of the transistors of the differential amplifier stage and of the dummy transistor.
In an advantageous embodiment, the measuring transistor has a greater collector area than the transistors of the differential amplifier stage. This ensures that the leakage current of the measuring transistor is always greater than the corresponding leakage current of the differential amplifier transistors and of the dummy transistor.
The current sources of the comparator are advantageously constructed as ideal current sources. Typically, however, the current sources are constructed as field-effect-controlled transistors, particularly as MOSFETs. As an alternative, an embodiment of the current sources as resistors would also be conceivable.
The differential input signal, which is coupled into the input terminals can be picked up in a very simple manner, for example, across a shunt resistor connected to an input terminal. The other input terminal in each case could then be connected, for example, to the potential of a reference ground.
The transistors of the differential amplifier stage and/or of the dummy transistor and/or of the measuring transistor are typically constructed as bipolar transistors. The transistors of the correction circuit and/or of the current sources could also be implemented in a bipolar manner. However, any other embodiment of these elements would also be conceivable. The transistors of the current balancing configurations, for example, can be constructed as MOSFETs equivalent to the transistors of the current sources. However, the current source transistors and the transistors of the current balancing configurations can also be constructed in another manner, for example by junction FET transistors, thyristors, IGBTs or the like.
In one embodiment, the first transistor and/or the second transistor of the differential amplifier stage are integrated in a semiconductor body, the transistors are implemented by connecting the load paths of a multiplicity of first and second single transistors in parallel. The best possible matching of the two transistors of the differential amplifier stage can be achieved in this case, for example, by so-called crossing out of the transistors in the layout. By crossing out it is meant that the respective transistors have the same center point or center of gravity in the layout. It is particularly in the implementation of the transistors via a parallel connection of a multiplicity of single-transistors that this can be achieved in that the center point of the individual transistors, which form the first and third transistor coincides with the center point of the individual transistors for the second transistor.
It is particularly advantageous if the multiple or, respectively, the area ratio of the first and third transistor with respect to the second transistor is equal or approximately equal to two. With n=2 and at room temperature, the offset is about 18 mV. In the case of a square, rectangular, strip-shaped or similar layout of the transistor areas, the three transistorsxe2x80x94i.e. the transistors of the differential amplifier stage and the dummy transistorxe2x80x94can be disposed here in a very simple manner next to one another, the second transistor being disposed between the other two. The first and third transistor thus indicate the center point of the second transistor in this case. Transistors with round, oval, hexagonal, triangular layouts would also be conceivable. In this case, the correspondingly best-suited transistor layouts could be selected according to the desired offset.
In accordance with an added feature of the invention, the effective area ratio is equal to a sum of effective collector areas of the first and the third transistor divided by an effective collector area of the second transistor.
In accordance with an additional feature of the invention, a correction circuit is provided and has a first output connected to the output of the first current source and a second output connected to the output of the second current source. In a case where a leakage current at one of the first and the second transistor exceeds the first operating current or the second operating current, respectively, the correction circuit dynamically superimposes a-correction current on one of the first and the second operating current in such a manner that a resultant current is greater than the leakage current.
In accordance with another feature of the invention, the correction circuit has two current balancing circuits including a first current balancing circuit and a second current balancing circuit. The two current balancing circuits have a common input branch and in each case one output branch.
A transmission ratio of the first current balancing circuit is inversely proportional to the effective collector area of the first and of the third transistor. A transmission ratio of the second current balancing circuit is inversely proportional to the effective collector area of the second transistor.
In accordance with a further feature of the invention, the correction circuit has a measuring transistor with a load current path disposed in the common input branch of the two current balancing circuits.
In accordance with a further added feature of the invention, the measuring transistor has an effective collector area that is greater than the effective collector area of the first transistor, the effective collector area of the second transistor, and/or the effective collector area of the third transistor.
In accordance with a further additional feature of the invention, at least one of the current sources is constructed from a transistor, including MOSFETs. Alternatively, at least one of the current sources is constructed as a resistor.
In accordance with another feature of the invention, a shunt resistor is connected to the second input terminal and across which an input voltage can be picked off.
In another alternative of the invention, a semiconductor body is provided and the first transistor, the second transistor, and/or the third transistor is integrated in the semiconductor body. Each of the first, the second and the third transistor is formed of three individual transistors having load current paths connected in parallel with each other. The three individual transistors include a first individual transistor, a second individual transistor and a third individual transistor. The first and the third individual transistor of the first and the third transistor and the second individual transistor of the second transistor are disposed in such a manner that a center point resulting from the first and the third individual transistor is equal to a center point of the at second individual transistor in a layout of the semiconductor body.
In accordance with a concomitant feature of the invention, the multiple is two.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a bipolar comparator, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.